1. Field of the Invention
The present invention relates to an address conversion apparatus for controlling DMA (Direct Memory Access) for data transfer between each I/O (Input/Output) device and the main storage in a computer system.
2. Description of the Prior Art
Heretofore, in the technology of address conversion, wherein a logical address delivered as an output from a central processing unit (CPU) is converted into a physical address, which is an actual memory address, and with which the main storage is accessed, there is a known technique wherein conversion means or a converter is provided for converting the output logical address of an input/output device (I/O device) into a physical address (hereinafter, such conversion shall be termed a "DMA address conversion") in an access whose transfer master is the I/O device, as in DMA (Direct Memory Access). An example of an application concerning the technique of DMA address conversion is disclosed in Japanese Patent Application Laid-open No. 193961/1989.
The prior-art technique mentioned above is devoid of a method in which the CPU accesses the main storage through the DMA address conversion means or converter. Therefore, in a case where a memory area to be accessed by the DMA is rewritten or referred to by an access from the CPU, the program of the CPU needs to manage the address conversion to provide the physical address.
Also, in a case where the output logical address of an I/O device is subjected to DMA address conversion, the overhead involved in referring to a conversion table for every DMA leads sometimes to the lowering of the data transfer rate, which cannot be ignored.
In this regard, Japanese Patent Application Laid-open No. 193961/1989 mentioned above teaches a technique wherein, as illustrated in FIG. 8, conversion index buffers (address conversion buffers) 29-1 through 29-n are disposed in correspondence with n I/O device channels 24-1 through 24-n.
Referring to FIG. 8, an output logical address 26 delivered from a CPU 103 is converted through an address converter 22 into a physical address 27, with which a main storage 510 is accessed.
The conversion index buffers 29-1.about.29-n are respectively disposed for the individual channel Nos. of the I/O device channels 24-1.about.24-n in one-to-one correspondence.
On the other hand, in a case where any of a first I/O device 31-1.about.an n-th I/O device 31-n accesses the main storage 510, the I/O device 31 produces an I/O device output address 25 in the form of a logical address. The output logical address 25 is converted into a DMA physical address 18 in accordance with the correspondence data items of logical page addresses and physical page addresses which are contained in the first conversion index buffer 29-1.about.the n-th conversion index buffer 29-n constituting a DMA address conversion apparatus 20.
When the pertinent logical page address is not contained in any of the conversion index buffers, an I/O device output page address 12 is delivered to a DMA page conversion table (DMA map) 114 and is converted into a physical page address 15 by this table.
Since the prior art arranges the conversion index buffers in correspondence with the respective channels of the I/O devices, it has had the problem that the quantity of hardware required for the conversion index buffers increases in a system having a large number of channels.